Wireless communication systems are well known and include various types of systems, such as cellular telephone systems, paging systems, two-way radio systems, personal communication systems, personal area networks, data systems, and various combinations thereof. Such wireless systems are known to include a system infrastructure and communication devices constructed and programmed to operate in the particular system. The system infrastructure includes fixed network equipment, such as base transceiver sites (BTSs), system controllers, switches, routers, communication links, antenna towers, and various other known infrastructure components. The communication devices include, inter alia, antenna systems, transmitters, receivers, processors, memory, user interfaces, and user controls.
In digital wireless communication systems, certain elements of the system, such as BTS or communication device receivers and/or BTS or communication device transmitters, typically include analog-to-digital (A/D) converters, digital-to-analog (D/A) converters, and/or digital-to-digital (D/D) converters depending upon the selected implementation of the system and its elements. Many such converters employ a sigma-delta architecture and are generally referred to as sigma-delta converters. Analog-to-digital converters of the sigma-delta architecture typically provide a coarse quantization analog-to-digital conversion of an input signal, resulting in a single bit output during each clock cycle. One such prior art sigma-delta converter 100 is depicted in electrical block diagram form in FIG. 1.
The sigma-delta converter 100 includes one or more feedback loops, each comprising a forward path and a feedback path. Each forward path includes one or more sets of serially connected summers 101, 102 and filters 104, 105, a comparator 107, and a storage device 109 docked typically at four Megahertz (4 MHz). The number of feedback loops (two shown) is equivalent to the number of summers 101, 102 and defines the order of the converter 100. The converter 100 of FIG. 1 is a second order sigma-delta converter.
The summers 101, 102 comprise conventional analog summers, the filters 104, 105 comprise conventional integrators, the comparator 107 comprises a conventional analog comparator, and the storage device 109 comprises one or more D flip-flops depending on the desired transfer function of the converter 100. For a lowpass converter, the storage device 109 typically comprises a single D flip-flop. For a bandpass converter, the storage device 109 typically comprises two cascaded D flip-flops 801, 802 in the arrangement depicted in FIG. 8. The filters 104, 105 reduce the quantization noise in the desired operating frequency band of the converter 100. For a typical lowpass converter 100, the filters 104, 105 reduce noise within a bandwidth of about 0-10 kilohertz (kHz).
Operation of the sigma-delta converter 100 occurs substantially as follows. An input signal source, such as a demodulator, provides an input signal 111 to summer 101. Summer 101 subtracts the input signal 111 from the clocked output signal 127 of the storage device 109 to produce error signal 113. Error signal 113 is averaged by filter 104 and averaged error signal 115 is applied to summer 102. Summer 102 subtracts averaged error signal 115 from the clocked output signal 127 of the storage device 109 to produce error signal 117. Error signal 117 is averaged by filter 105 and averaged error signal 119 is applied to the positive input of the comparator 107.
The comparator 107 compares averaged error signal 119 to a predetermined reference level 121 (e.g., signal ground) and produces a comparison result signal 123 based on the comparison. The comparison result signal 123 is applied to the storage device 109, where it is stored for a delay period (e.g., a clock cycle) and output responsive to a dock signal 125. The clocked output signal 127 of the storage device 109 forms the single bit output of the sigma-delta converter 100 and is typically applied to a signal processor. The negative feedback loops of the converter 100 force the average of the single bit output 127 of the converter 100 to accurately represent the input 111 despite the coarseness of the instantaneous approximation.
For large input signals 111, such as those greater than or equal to about one-half the full scale voltage level that can be accepted by the converter 100 without introducing nonlinear distortion, the converter 100 of FIG. 1 functions very well as illustrated in FIGS. 2 and 3. FIGS. 2 and 3 are broadband and narrowband spectral diagrams 200, 300, respectively, of the amplitude of a Fast Fourier Transform (FFT) performed on the output signal 127 of the converter 100 for a 10 kHz, relatively large amplitude (e.g., one-half full scale) input signal 111. As depicted in FIG. 2, the average broadband noise of the converter 100 remains relatively flat at −60 decibels above one volt (dBV) and, as depicted in FIG. 3, the average in-band noise (i.e., the noise in the range of 0-10 kHz) is more than 110 dB below the input signal level.
Although the sigma-delta converter 100 of FIG. 1 performs well for large-scale input signals 111, it performs poorly for input signals 111 near the low end of the converter's dynamic range (e.g., approximately one one-hundredth or less of the full scale voltage level that can be accepted by the converter 100). Such low-level input signals 111 can generate repeating output bit patterns that create in-band idle tones in the converter's output signal 127. The presence of in-band idle tones is illustrated in FIGS. 4 and 5. FIGS. 4 and 5 are broadband and narrowband spectral diagrams 400, 500, respectively, of the amplitude of an FFT performed on the output signal 127 of the converter 100 for a 10 kHz, relatively small amplitude (e.g., {fraction (1/500)}th full scale) input signal 111. As depicted in FIG. 4, the average broadband noise of the converter 100 still remains relatively flat at −50 dBV. However, as depicted in FIG. 5, idle tones 501 at integer multiples of 2 kHz significantly degrade the signal-to-noise performance of the converter 100. Such tones may cause the automatic frequency control (AFC) system of a communications receiver to falsely lock on an idle tone 501 instead of the desired signal.
To substantially reduce the levels of the idle tones 501, conventional communications devices employ a dither signal generator 129 to generate an out-of-band dither signal 131 with which to continuously drive the sigma-delta converter 100. The dither signal generator 129 may be an out-of-band tone generator or a complicated circuit that generates pseudo-random noise sequences. The dither signal amplitude is typically sufficient to keep the converter 100 operating under large signal conditions, regardless of the input signal level of the desired in-band signal 111. By maintaining large signal converter operation, the dither signal 131 reduces the in-band idle tones as illustrated in FIGS. 6 and 7.
FIGS. 6 and 7 are broadband and narrowband spectral diagrams 600, 700, respectively, of the amplitude of an FFT performed on the output signal 127 of the converter 100 for a 10 kHz, relatively small amplitude input signal 111 under the same conditions as in FIGS. 4 and 5, and a 125 kHz dither signal 131 of substantially larger amplitude than the amplitude of the input signal 111. With respect to the graphs 600, 700 of FIGS. 6 and 7, the dither signal amplitude is approximately {fraction (1/12)} the full scale amplitude that can be accepted by the converter 100 without introducing nonlinear distortion. As depicted in FIG. 6, FFT amplitude peaks are evident at integer multiples of the dither signal frequency (i.e., 125 kHz). The amplitude peaks indicate the presence of the dither signal 131 in the converter output 127. As shown in FIG. 7, the dither signal 131 functions to reduce the amplitudes of the idle tones 701 for low-level input signals 111 as compared to the amplitudes of the idle tones 501 without use of such a dither signal 131 as in FIG. 5. A comparison of FIG. 7 to FIG. 5 (both of which were generated under the same input conditions) shows that the addition of the dither signal 131 reduces the in-band idle tone signal level by approximately 17 dB (i.e., from about 43 dB below the input signal level of −60 dBV to about 60 dB below the input signal level).
However, the idle tone amplitude reduction provided by the externally-applied dither signal 131 does not occur without a cost. The addition of the dither signal 131 can cause a spurious response signal in a radio frequency (RF) operating band of a communication device when the converter 100 and the dither signal generator 129 are incorporated into a receiver or transmitter of such a device. The dither signal 131 can heterodyne or mix with RF signals of the communication system in which the communication device operates to produce an in-band RF product. Such an in-band RF product can compromise the spurious response specification of the communication device. Increasing the frequency of the dither signal 131 (e.g., to 1 MHz) typically reduces the influence of the RF spurious signal by effectively moving the spurious signal out of the RF operating band of the communication device. However, such an increase in dither signal frequency also reduces the effectiveness of the dither signal 131 in reducing the levels of the idle tones 501, 701 because, at higher frequencies, the dither signal 131 becomes less distinguishable from the elevating noise floor.
Therefore, a need exists for a sigma-delta converter that provides improved in-band signal-to-noise performance for low-level input signals without requiring the use of an external dither signal. There is a further need for a communication device that incorporates such a sigma-delta converter to perform A/D, D/D, and/or D/A conversion without degrading spurious response performance of the device.